The integration of micro-scale or nano-scale semiconductor devices into multifunction systems is one of the main challenges in the field of semiconductor packaging. The challenge arises from the incompatibility of fabrication steps required for manufacturing different semiconductor devices. As a result of this incompatibility, the monolithic integration approach, where devices are manufactured in a common substrate, cannot be followed. Therefore, in a heterogeneous functional system the semiconductor devices are manufactured separately and assembled at a later stage to form a multifunction system.
Robotic “pick-and-place” is a commonly adopted method for assembling and packaging separate semiconductor devices into functional systems. This technique has been used in the integration of large scale semiconductor devices and has been proven to be both accurate and reliable. However, as semiconductor device dimensions continue to shrink, this assembling technique becomes less preferable. A main disadvantage of the robotic pick-and-place method is that it does not offer the required accuracy for assembling small semiconductor devices comprising hundreds or even thousands of fine-pitch micro-bumps. In addition, given the serial nature of the robotic pick-and-place technique, the throughput is considerably low, thereby making the overall process of forming a multifunction system expensive.
An alternative packaging solution to the robotic pick-and-place is the self-assembly (“SA”) of semiconductor devices. The use of SA allows the autonomous organization of components into ordered patterns and structures without human intervention. As a result, SA is parallel in nature and can be applied to a wide range of semiconductor device dimensions
Fukushima et al. [Fukushima, T.; Ohara, Y.; Murugesan, M.; Bea, J.-C.; Lee, K.-W.; Tanaka, T.; Koyanagi, M.; “Self-Assembly Technologies with High-Precision Chip Alignment and Fine-Pitch Microbump Bonding for Advanced Die-to-Wafer 3D Integration,” Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st, vol., no., pp. 2050-2055, May 31, 2011-Jun. 3 2011] describes such an SA method of semiconductor substrates with indium/gold micro-bump arrays formed on a bonding surface. However, the precise alignment of the semiconductor substrate is still an issue. This is because the precise alignment of the semiconductor substrates is highly dependent on the formation on the hydrophobic regions with respect to the fine-pitch micro-bumps. As a result errors during formation of the hydrophobic regions may result in miss-alignment between the droplet confinement, which is controlled by the hydrophobic region, and the micro-bumps. This miss-alignment is of particular concern to the assembly of semiconductor devices with fine pitch micro-bumps. Such a miss-alignment can cause shorts or weak connections between fine-pitch micro-bumps, thereby compromising the yield of the functional system. Moreover, the method presented does not provide any provisions for protecting from oxidization micro-bumps comprising oxidizing material that are commonly used in semiconductor fabrication. A further shortcoming of the proposed SA method is the use of thermo-compression for permanently bonding the semiconductor substrates, which can compromise the yield of certain semiconductor substrates that contain devices sensitive to high temperatures and forces applied during this step. In addition, the final thermal compression at elevated temperature can cause some misalignment due to coefficient of thermal expansion (“CTE”) mismatch.
Therefore, there is a need for providing an SA method that offers high assembly accuracy of devices with fine-pitch micro-bumps and is compatible with conventional processing flows.